Metal-insulator-semiconductor (MIS) devices such as MIS capacitors and MIS field effect transistors (MISFET), are utilized in a wide variety of applications, including test structures, and digital and analog applications in integrated circuit technology. An MIS device typically consists of a semiconductor substrate, such as a silicon (Si) substrate which has been doped with either an n-type dopant, such as phosphorus, or a p-type dopant, such as boron. An MIS device also includes an insulating layer, typically formed by an oxide such as silicon dioxide (SiO.sub.2), which is grown or deposited on one surface of the semiconductor substrate. Finally, a layer of conductive material, such as degenerately doped polysilicon or a metal, is deposited on the surface of the insulating layer, opposite the semiconductor layer. Because the insulator is typically oxide, these devices are also referred to as metal-oxide-semiconductors (MOS) devices.
Electrical contacts may thereafter be formed to the metal or degenerate polysilicon layer and to the surface of the semiconductor layer opposite the insulating layer to produce a MIS capacitor. The electrode to the metal or degenerate polysilicon layer is generally referred to as the gate electrode and the electrode to the semiconductor layer is generally referred to as the semiconductor substrate electrode. Source and drain contacts may also be formed to laterally spaced apart regions of the semiconductor layer on opposite sides of the metal and insulating layers to produce a MISFET.
Due, in part, to the importance and widespread use of MIS devices, several methods have been proposed for approximating several parameters of the MIS devices which, in turn, predict the characteristics and operating performance of MIS devices. The parameters which determine the performance of an MIS device are related to or are dependent upon the process by which the MIS device is fabricated and include the threshold voltage of the MIS device which depends upon the doping density profile of the semiconductor layer, the thickness of the insulating layer, the fixed charge density of the insulating layer, the interface trap density and the voltage across a depleted semiconductor layer upon the application of a bias voltage between the gate electrode and the semiconductor layer. Accordingly, the parameters of a MIS device may be analyzed to determine if the device will perform satisfactorily.
One or more of these parameters is typically estimated based upon an analysis of the capacitance-voltage (C-V) characteristics of a MIS device. The C-V characteristics of a MIS device are determined by applying varying voltages, typically referred to as bias voltages, between the gate and semiconductor substrate electrodes and measuring the resulting capacitance of the insulating and semiconductor layers. The bias voltage generally includes a DC voltage upon which an AC voltage is superimposed. The DC voltage is incrementally varied such that the MIS device operates successively in an accumulation mode and a depletion mode.
In accumulation mode, the majority carrier concentration, i.e., the electron carrier concentration for an n-doped semiconductor layer, is greater near the interface of the insulating and semiconductor layers than in the bulk region of the semiconductor layer removed from the interface. In contrast, in depletion mode, the electron and hole concentrations at the interface of the insulating and semiconductor layer is less than determined by the doping concentration in the bulk region of the semiconductor layer.
The energy levels and relaxation times of interface traps at an Si--SiO.sub.2 interface were calculated based upon the C-V characteristics of a metal-oxide-semiconductor (MOS) device measured over a wide range of frequencies as reported by L. M. Terman, Solid-State Electronics, Vol. 5, p. 285 (1962) and K. Lekovec, et al., Phys. Stat. Solids, Vol. 3, p. 447 (1963). The interface trap density of an MOS capacitor has also been determined, as a function of Si bandgap energy, from C-V measurements obtained with a slowly varying DC bias voltage ramp. See C. N. Berglund, IEEE Transactions Electronic Devices, Vol. ED-13, 701 (1966).
The interface trap density of a MOS capacitor as a function of the Si bandgap energy was also obtained from C-V measurements employing AC signals having both a relatively high frequency and a relatively low frequency which are superimposed upon a DC bias voltage. See R. Costagne, et al., Surface Science, Vol. 28, p. 557 (1971). For example, a varying DC signal having a relatively high frequency AC signal superimposed thereon could be applied between the gate and semiconductor substrate electrodes. Thereafter, a varying DC signal having a relatively low frequency AC signal superimposed thereon could be applied between the gate and semiconductor substrate electrodes such that C-V measurements could be obtained for bias voltages having both high and low frequency AC signal components superimposed thereon.
An alternative method, referred to as a conductance method, for determining the electrical properties of interface traps at the Si--SiO.sub.2 interface was proposed by the present inventor E. H. Nicollian and A. Goetzberger, Bell System Tech. J., Vol. 46, p. 1055 (1967). According to the conductance method, a bias voltage having both DC and AC components is applied. Thereafter, the admittance measured between the gate electrode and the semiconductor substrate electrode is measured as a function of both the amplitude of the bias voltage and the frequency of the AC signal superimposed thereon. Based upon the measured admittance, the interface trap density may be calculated.
As disclosed by W. Van Gelder and E. H. Nicollian in the Journal of the Electrochemical Society, Vol. 118, p. 138 (1971), a doping density profile of the semiconductor layer near an Si--SiO.sub.2 interface may be approximated based upon the C-V characteristics of a MOS capacitor. Subsequently, a charge-capacitance (Q-C) method was proposed by J. R. Brews and E. H. Nicollian in Solid-State Electronics, Vol. 27, p. 963 (1984). The Q-C method includes a C-V measurement performed with a relatively high frequency AC signal superimposed upon a varying DC bias voltage. A charge-voltage (Q-V) measurement is then obtained by applying a varying DC bias voltage and measuring the resulting change in charge across the oxide and semiconductor layers of the MOS capacitor. From the C-V and Q-V measurements, the process-dependent parameters of the MIS device could be approximated.
The Q-C method proposed by J. R. Brews and E. H. Nicollian, however, does not uniquely yield the parameters that quantitatively determine the doping profile, nor does it measure the doping profile of the semiconductor layer near the interface of the insulating and semiconductor layers since the charge neutrality principle upon which the Q-C method is based does not apply near the interface. For example, in a p-doped semiconductor layer, the hole density near the interface of the insulating and semiconductor layers is not equal to the acceptor density at a given depth from the interface.
Since the doping density profile near the interface of the insulating and semiconductor layers is not measured by the Q-C method, the doping density profile near the interface is extrapolated. This extrapolation is based upon fitting the doping density profile of the semiconductor layer in regions spaced apart from the insulating-semiconductor interface in which the charge neutrality principle is applicable with a profile function known from the processing, such as a Gaussian or error function compliment profile. Therefore, while the doping density profile of the semiconductor layer near the insulating-semiconductor interface may be extrapolated in this manner, a unique set of parameters that define the fitted profile function is difficult to obtain since numerous estimates of the doping density profile of the semiconductor layer are possible.
It is desirable to reliably determine the true doping density profile and the process-related parameters of a semiconductor layer, such as found in an MIS device, such that the operating characteristics or performance of the semiconductor layer or MIS device may be reliably predicted. Various methods and systems have been proposed for approximating one or more of the process-related parameters based upon C-V and/or Q-V measurements of an MIS device. These methods and systems, however, are limited in reliability or are not quantitative.